Crossbar Switch (XBAR)
MPC5606S Microcontroller Reference Manual, Rev. 7
280 Freescale Semiconductor
priority master and grants it ownership of the slave port. All other masters requesting that slave port are
stalled until the higher priority master completes its transactions.
Requesting masters are granted access based on a fixed priority. A block diagram of the XBAR is shown
in Figure 10-1.
10.4 Features
• Four Master ports:
— core: e200z0h core instructions
— core: e200z0h core data / Nexus
—eDMA
— Display Controller Unit (DCU)
• Six slave ports
— PFlash-CPU
— PFlash-DCU
— Internal SRAM
— Graphics SRAM
— Peripheral bridge (PBRIDGE)
— QuadSPI
• 32-bit address, 32-bit data paths
• Fully concurrent transfers between independent master and slave ports
• Fixed priority scheme and fixed parking strategy
10.5 Modes of operation
10.5.1 Normal mode
In normal mode, the XBAR provides the logic that controls crossbar switch configuration.
10.5.2 Debug mode
The XBAR operation is unchanged when the CPU has debug mode active.
10.6 Functional description
This section describes the functionality of the XBAR in more detail.
10.6.1 Overview
The main goal of the XBAR is to increase overall system performance by allowing multiple masters to
communicate concurrently with multiple slaves. To maximize data throughput, it is essential to keep
arbitration delays to a minimum.
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