NXP Semiconductors MPC5606S - Flash ECC Master Number Register (FEMR)

Error Correction Status Module (ECSM)
MPC5606S Microcontroller Reference Manual, Rev. 7
536 Freescale Semiconductor
16.4.2.12 Flash ECC Master Number Register (FEMR)
The FEMR is a 4-bit register for capturing the XBAR bus master number of the last properly enabled ECC
event in the flash memory. Depending on the state of the ECC Configuration Register, an ECC event in
the flash memory causes the address, attributes, and data associated with the access to be loaded into the
FEAR, FEMR, FEAT, and FEDR registers, and the appropriate flag (F1BC or FNCE) in the ECC Status
Register to be asserted.
This register can only be read from the IPS programming model; any attempted write is ignored. See
Figure 16-11 and Table 16-12 for the Flash ECC Master Number Register definition.
16.4.2.13 Flash ECC Attributes (FEAT) register
The FEAT is an 8-bit register for capturing the XBAR bus master attributes of the last properly enabled
ECC event in the flash memory. Depending on the state of the ECC Configuration Register, an ECC event
in the flash memory causes the address, attributes, and data associated with the access to be loaded into
the FEAR, FEMR, FEAT, and FEDR registers, and the appropriate flag (F1BC or FNCE) in the ECC Status
Register to be asserted.
This register can only be read from the IPS programming model; any attempted write is ignored. See
Figure 16-12 and Table 16-13 for the Flash ECC Attributes Register definition.
Table 16-11. Flash ECC Address (FEAR) field descriptions
Name Description
0-31
FEAR[0:31]
Flash ECC Address Register
This 32-bit register contains the faulting access address of the last properly enabled flash memory
ECC event.
Address: Base + 0x0056 Access: User read-only
0 1 2 3 4 5 6 7
R 0 0 0 0 FEMR[0:3]
W
Reset —
1
1
Value is undefined at reset.
— — — — — — —
Figure 16-11. Flash ECC Master Number Register (FEMR)
Table 16-12. Flash ECC Master Number (FEMR) field descriptions
Name Description
4-7
FEMR[0:3]
Flash ECC Master Number Register
This 4-bit register contains the XBAR bus master number of the faulting access of the last properly
enabled flash memory ECC event.