LCD Driver (LCD64F6B)
MPC5606S Microcontroller Reference Manual, Rev. 7
812 Freescale Semiconductor
22.4.2.21 LCDRAM (Location 15)
22.5 Functional description
22.5.1 Frontplane, backplane, and LCD system during reset
During a reset the following conditions exist:
• All frontplane enable bits, FP[n-1:0]EN are cleared and the ON/OFF control for the display, the
LCDEN bit is cleared, thereby forcing all frontplane and backplane driver outputs to the high
impedance state. The pin state during reset is defined by the port control module.
Address: Base + 0x5C Access: User read/write
0 1 2 3 4 5 6 7
R 0 0
FP60BP5 FP60BP4 FP60BP3 FP60BP2 FP60BP1 FP60BP0
W
Reset 0 0 0 0 0 0 0 0
8 9 10 11 12 13 14 15
R 0 0
FP61BP5 FP61BP4 FP61BP3 FP61BP2 FP61BP1 FP61BP0
W
Reset 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23
R 0 0
FP62BP5 FP62BP4 FP62BP3 FP62BP2 FP62BP1 FP62BP0
W
Reset 0 0 0 0 0 0 0 0
24 25 26 27 28 29 30 31
R 0 0
FP63BP5 FP63BP4 FP63BP3 FP63BP2 FP63BP1 FP63BP0
W
Reset 0 0 0 0 0 0 0 0
Figure 22-22. LCDRAM (Location 15)
Table 22-26. LCDRAM (Location 15) field descriptions
Field Description
0:31 FP[60:63]BP[5:0]. LCD segment ON.
The FP[60:63]BP[5:0] bit displays (turns on) the LCD segment connected between FP[60:63] and BP[5:0].
0 LCD segment OFF
1 LCD segment ON0LCD segment OFF
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