NXP Semiconductors MPC5606S - Memory Map

Clock Description
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 217
8.9.4 Memory map
Table 8-20 shows the memory map locations. Addresses are given as offsets of the module base address.
NOTE
FMPLL_x registers are mapped through the MC_CGM register slot.
8.9.5 Register description
The PLL operation is controlled by two registers. Those registers can only be written in supervisor mode.
8.9.5.1 Control Register (CR)
Table 8-20. FMPLL Memory map
Address Register Access Location
Base:
0xC3FE00A0 (FMPLL0)
0xC3FE00C0 (FMPLL1)
0x0000 Control Register (CR) R/W on page 217
0x0004 Modulation Register (MR) Special on page 220
Offset 0x0000 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0
IDF ODF
0
NDIV
W
Reset 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
0 0 0 0 0 0 0
en_pl
l_sw
mod
e
unloc
k_on
ce
0
i_loc
k
s_loc
k
pll_fa
il_ma
sk
pll_fa
il_fla
g
0
W w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 Reset value is determined by the SoC integration.
Figure 8-24. Control Register (CR)