Clock Description
MPC5606S Microcontroller Reference Manual, Rev. 7
218 Freescale Semiconductor
Table 8-21. CR field descriptions
Field Description
2–5
IDF
The value of this field sets the PLL Input division factor as described in Table 8-22. The reset value
is set during integration.
6–7
ODF
The value of this field sets the PLL Output division factor as described in Ta ble 8-23. The reset value
is set during integration.
9–15
NDIV
The value of this field sets the PLL Loop division factor as described in Table 8-24. The reset value
is set during integration.
23
en_pll_sw
This bit is used to enable progressive clock switching. After the PLL locks, the PLL output initially is
divided by 8 then progressively divides down until divide by 1.
0 Progressive clock switching disabled
1 Progressive clock switching enabled
Note: The PLL output should not be used if a non-changing clock is needed (such as for serial
communications) until the division has finished.
24
mode
This bit activates the 1:1 mode.
25
unlock_once
This bit is a sticky indication of PLL loss-of-lock condition. The unlock_once bit is set when the PLL
loses lock. Whenever the PLL reacquires lock, unlock_once remains set. Only a power-on reset can
clear this bit.
Note: If the FMPLL is locked and a functional reset occurs, FMPLL_CR[UNLOCK_ONCE] is
automatically set even when the FMPLL has not lost lock.
27
i_lock
This bit is set by hardware whenever there is a lock/unlock event.It is cleared by software, writing 1.
28
s_lock
This bit indicates whether the PLL has acquired lock.
0 PLL unlocked
1 PLL locked
29
pll_fail_mask
This bit is used to mask the pll_fail output.
0 pll_fail not masked
1 pll_fail masked
30
pll_fail_flag
This bit is asynchronously set by hardware whenever a loss of lock event occurs while PLL is
switched on. It is cleared by software, writing 1.
Table 8-22. Input divide ratios
IDF[3:0] Input divide ratios
0000 Divide by 1
0001 Divide by 2
0010 Divide by 3
0011 Divide by 4
0100 Divide by 5
0101 Divide by 6
0110 Divide by 7
0111 Divide by 8
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