NXP Semiconductors MPC5606S - Soft Lock L1_TRANSP Register

Display Control Unit (DCU)
MPC5606S Microcontroller Reference Manual, Rev. 7
402 Freescale Semiconductor
Figure 12-54. Soft Lock L0_TRANSP Register
12.3.4.46 Soft Lock L1_TRANSP Register
Figure 12-55 represents the Soft Lock L1_TRANSP register.
Offset: 0x318 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0
SLB_L0_FCOLOR
SLB_L0_BCOLOR
0 0 0 0 0 0 0 0 0 0
W
WEN_L0_FCOLOR
WEN_L0_BCOLOR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 12-49. Soft Lock L0_TRANSP Register field descriptions
Field Description
0
WEN_L0_FCOLO
R
Write Enable for Soft Lock Bit SLB_L0_FCOLOR
0 SLB is not modified
1 Value is written to SLB
1
WEN_L0_BCOLO
R
Write Enable for Soft Lock Bit SLB_L0_BCOLOR
0 SLB is not modified
1 Value is written to SLB
4
SLB_L0_FCOLOR
Soft Lock Bit for L0_FCOLOR Register.
0 Associated protected register is not locked and writeable
1 Associated protected register is locked for write access
5
SLB_L0_BCOLOR
Soft Lock Bit for L0_BCOLOR Register.
0 Associated protected register is not locked and writeable
1 Associated protected register is locked for write access