FlexCAN
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 677
18.3.3 Rx FIFO Structure
When the FEN bit is set in the MCR, the memory area from 0x80 to 0xFF (which is normally occupied by
MBs 0 to 7) is used by the reception FIFO engine. Figure 18-3 shows the Rx FIFO data structure. The
region 0x0–0xC contains an MB structure which is the port through which the CPU reads data from the
FIFO (the oldest frame received and not read yet). The region 0x10–0xDF is reserved for internal use of
the FIFO engine. The region 0xE0–0xFF contains an 8-entry ID table that specifies filtering criteria for
accepting frames into the FIFO. Figure 18-4 shows the three different formats that the elements of the ID
table can assume, depending on the IDAM field of the MCR. Note that all elements of the table must have
the same format. See Section 18.4.7, Rx FIFO for more information.
0 1010 1010 Transmit a data frame whenever a remote request frame with the
same ID is received. This MB participates simultaneously in both
the matching and arbitration processes. The matching process
compares the ID of the incoming remote request frame with the ID
of the MB. If a match occurs this MB is allowed to participate in the
current arbitration process and the Code field is automatically
updated to 1110 to allow the MB to participate in future arbitration
runs. When the frame is eventually transmitted successfully, the
Code automatically returns to 1010 to restart the process again.
0 1110 1010 This is an intermediate code that is automatically written to the MB
by the MBM as a result of match to a remote request frame. The
data frame will be transmitted unconditionally once and then the
code will automatically return to 1010. The CPU can also write this
code with the same effect.
Table 18-6. Message Buffer Code for Tx Buffers (continued)
RTR
Initial Tx
code
Code after
successful
transmission
Description
To Next Page
Loading...
