NXP Semiconductors MPC5606S - Mask PARR_ERR Status Register

Display Control Unit (DCU)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 387
12.3.4.29 Mask PARR_ERR Status register
Figure 12-38 shows the mask register for parameter error status register.
Figure 12-38. Mask parameter error status register
30
L1_PARR_ERR
Interrupt occurs whenever there is an error in layer 1.
0 Parameter error is not set
1 Parameter error is set
31
L0_PARR_ERR
Interrupt occurs whenever there is an error in layer 0.
0 Parameter error is not set
1 Parameter error is set
Offset: 0x230 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0
M_HWC_ERR
M_SIG_ERR
M_DISP_ERR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
M_L15_parr_err M_L14_parr_err M_L13_parr_err M_L12_parr_err M_L11_parr_err M_L10_parr_err
M_L9_parr_err M_L8_parr_err M_L7_parr_err M_L6_parr_err M_L5_parr_err M_L4_parr_err M_L3_parr_err M_L2_parr_err M_L1_parr_err M_L0_parr_err
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Table 12-33. Mask parameter error status register field descriptions
Field Description
13
M_HWC_ERR
M_HWC_ERR interrupt mask
0 Do not mask the interrupt
1 Mask the interrupt
14
M_SIG_ERR
M_SIG_ERR interrupt mask
0 Do not mask the interrupt
1 Mask the interrupt
15
M_DISP_ERR
M_DISP_ERR interrupt mask
0 Do not mask the interrupt
1 Mask the interrupt
16
M_L15_parr_err
M_L15_parr_err interrupt mask
0 Do not mask the interrupt
1 Mask the interrupt
Table 12-32. Parameter Error Status Register field descriptions (continued)
Field Description