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NXP Semiconductors MPC5606S - Selecting an IEEE 1149.1-2001 Register

NXP Semiconductors MPC5606S
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IEEE 1149.1 Test Access Port Controller (JTAGC)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 723
19.8.3.1 Selecting an IEEE 1149.1-2001 register
Access to the JTAGC data registers is done by loading the instruction register with any of the JTAGC
instructions while the JTAGC is enabled. Instructions are shifted in via the select-IR-scan path and loaded
in the Update-IR state. At this point, all data register access is performed via the select-DR-scan path.
The select-DR-scan path is used to read or write the register data by shifting in the data (LSB first) during
the shift-DR state. When reading a register, the register value is loaded into the IEEE 1149.1-2001 shifter
during the capture-DR state. When writing a register, the value is loaded from the IEEE 1149.1-2001
shifter to the register during the Update-DR state. When reading a register, there is no requirement to shift
out the entire register contents. Shifting can be terminated after fetching the required number of bits.
19.8.4 JTAGC instructions
This section gives an overview of each instruction. Refer to the IEEE 1149.1-2001 standard for more
details.
The JTAGC implements the IEEE 1149.1-2001 defined instructions listed in Table 19-3.
Table 19-4 shows the implementation for silicon cut1. By mistake, the Access to Nexus Port Controller is
not using the standard PowerPC instruction.
For silicon cut2, the instruction coding will be changed to be 100% compatible with existing PowerPC.
Table 19-3. JTAG instructions
Instruction Code[4:0] Instruction summary
IDCODE 00001 Selects device identification register for shift
SAMPLE/PRELOAD 00010 Selects boundary scan register for shifting, sampling, and preloading
without disturbing functional operation
SAMPLE 00011 Selects boundary scan register for shifting and sampling without
disturbing functional operation
EXTEST 00100 Selects boundary scan register while applying preloaded values to output
pins and asserting functional reset
ACCESS_AUX_TAP_TCU 11011 Grants the TCU ownership of the TAP
ACCESS_AUX_TAP_ONCE 10001 Grants the PLATFROM ownership of the TAP
ACCESS_AUX_TAP_NPC 10000 Grants the Nexus port controller (NPC) ownership of the TAP
BYPASS 11111 Selects bypass register for data operations
Factory Debug Reserved
1
1
Intended for factory debug, and not customer use
00101
00110
01010
Intended for factory debug only
Reserved
2
2
Freescale reserves the right to change the decoding of reserved instruction codes
All Other Codes Decoded to select bypass register

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