NXP Semiconductors MPC5606S - ECC Status Register (ESR)

Error Correction Status Module (ECSM)
MPC5606S Microcontroller Reference Manual, Rev. 7
530 Freescale Semiconductor
The reporting of single-bit memory corrections can only be enabled via an SoC-configurable module input
signal. While not directly accessible by a user, this capability is viewed as important for error logging and
failure analysis.
See Figure 16-7 and Table 16-8 for the ECC Configuration Register definition.
16.4.2.9 ECC Status Register (ESR)
The ECC Status Register is an 8-bit control register for signaling which types of properly enabled ECC
events have been detected. The ESR signals the last properly enabled memory event to be detected. ECC
interrupt generation is separated into single-bit error detection/correction, uncorrectable error detection,
Address: Base + 0x0043 Access: User read/write
0 1 2 3 4 5 6 7
R 0 0
ER1BR EF1BR
0 0
ERNCR EFNCR
W
Reset 0 0 0 0 0 0 0 0
Figure 16-7. ECC Configuration Register (ECR)
Table 16-8. ECC Configuration (ECR) field descriptions
Name Description
2
ER1BR
Enable RAM 1-bit Reporting
0 Reporting of single-bit RAM corrections is disabled.
1 Reporting of single-bit RAM corrections is enabled.
This bit can only be set if the SoC-configurable input enable signal is asserted. The occurrence of a
single-bit RAM correction generates an ECSM ECC interrupt request as signaled by the assertion of
ESR[R1BC]. The address, attributes, and data are also captured in the REAR, RESR, REMR, REAT,
and REDR registers.
3
EF1BR
Enable Flash 1-bit Reporting
0 Reporting of single-bit flash memory corrections is disabled.
1 Reporting of single-bit flash memory corrections is enabled.
This bit can only be set if the SoC-configurable input enable signal is asserted. The occurrence of a
single-bit flash memory correction generates an ECSM ECC interrupt request as signaled by the
assertion of ESR[F1BC]. The address, attributes, and data are also captured in the FEAR, FEMR,
FEAT, and FEDR registers.
6
ERNCR
Enable RAM Non-Correctable Reporting
0 Reporting of non-correctable RAM errors is disabled.
1 Reporting of non-correctable RAM errors is enabled.
The occurrence of a non-correctable multi-bit RAM error generates an ECSM ECC interrupt request as
signaled by the assertion of ESR[RNCE]. The faulting address, attributes, and data are also captured
in the REAR, RESR, REMR, REAT, and REDR registers.
7
EFNCR
Enable Flash Non-Correctable Reporting
0 Reporting of non-correctable flash memory errors is disabled.
1 Reporting of non-correctable flash memory errors is enabled.
The occurrence of a non-correctable multi-bit flash memory error generates an ECSM ECC interrupt
request as signaled by the assertion of ESR[FNCE]. The faulting address, attributes, and data are also
captured in the FEAR, FEMR, FEAT, and FEDR registers.