Error Correction Status Module (ECSM)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 531
last properly enabled memory event, and the combination of the two as defined by the following Boolean
equations. In these equations, “&” refers to a bitwise AND operator, and “|” refers to a bitwise OR
operator; bitwise AND has precedence over bitwise OR.
ECSM_ECC1BIT_IRQ
= ECR[ER1BR] & ESR[R1BC]// RAM, 1-bit correction
| ECR[EF1BR] & ESR[F1BC]// Flash, 1-bit correction
ECSM_ECCRNCR_IRQ
= ECR[ERNCR] & ESR[RNCE]// RAM, noncorrectable error
ECSM_ECCFNCR_IRQ
= ECR[EFNCR] & ESR[FNCE]// Flash, noncorrectable error
ECSM_ECC2BIT_IRQ
= ECSM_ECCRNCR_IRQ// RAM, noncorrectable error
| ECSM_ECCFNCR_IRQ// Flash, noncorrectable error
ECSM_ECC_IRQ
= ECSM_ECC1BIT_IRQ // 1-bit correction
| ECSM_ECC2BIT_IRQ// noncorrectable error
where the combination of a properly enabled category in the ECR and the detection of the corresponding
condition in the ESR produces the interrupt request.
The ECSM allows a maximum of one bit of the ESR to be asserted at any given time. This preserves the
association between the ESR and the corresponding address and attribute registers, which are loaded on
each occurrence of a properly enabled ECC event. If there is a pending ECC interrupt and another properly
enabled ECC event occurs, the ECSM hardware automatically handles the ESR reporting, clearing the
previous data and loading the new state, thus guaranteeing that only a single flag is asserted.
To maintain the coherent software view of the reported event, the following sequence in the ECSM error
interrupt service routine is recommended:
1. Read the ESR and save it.
2. Read and save all the address and attribute reporting registers.
3. Re-read the ESR and verify the current contents match the original contents. If the two values are
different, go back to step 1 and repeat.
4. When the values are identical, write a 1 to the asserted ESR flag to negate the interrupt request.
See Figure 16-8 and Table 16-9 for the ECC Status Register definition.
Address: Base + 0x0047 Access: User read/write
0 1 2 3 4 5 6 7
R 0 0 R1BC F1BC 0 0 RNCE FNCE
W w1c w1c w1c w1c
Reset 0 0 0 0 0 0 0 0
Figure 16-8. ECC Status Register (ESR)
To Next Page
Loading...
