Safety
MPC5606S Microcontroller Reference Manual, Rev. 7
124 Freescale Semiconductor
4.2.5.4 SWT Timeout Register (SWT_TO)
The SWT Timeout (SWT_TO) register contains the 32-bit timeout period. This register is read only if
either the SWT_CR[HLK] or SWT_CR[SLK] bits are set.
The default counter value (SWT_TO_RST) is 1280 (0x500 hexadecimal), which corresponds to 10 ms
with a 128 kHz clock.
Address: Base + 0x0004 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIF
W w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 4-13. SWT Interrupt Register (SWT_IR)
Table 4-8. SWT_IR field descriptions
Field Description
TIF Timeout Interrupt Flag. The flag and interrupt are cleared by writing a 1 to this bit. Writing a 0 has no
effect.
0 No interrupt request.
1 Interrupt request due to an initial timeout.
Address: Base + 0x0008 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
WTO[31:16]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
WTO[15:0]
W
Reset 1 1 1 1 1 1 0 1 1 1 1 0 0 0 0 0
Figure 4-14. SWT Timeout Register (SWT_TO)
Table 4-9. SWT_TO Register field descriptions
Field Description
WTO Watchdog timeout period in clock cycles. An internal 32-bit down counter is loaded with this value or
0x100, whichever is greater, when the service sequence is written or when the SWT is enabled.
To Next Page
Loading...
