Enhanced Direct Memory Access (eDMA)
MPC5606S Microcontroller Reference Manual, Rev. 7
478 Freescale Semiconductor
15.3.1 Register descriptions
15.3.1.1 DMA Control Register (DMACR) register
The 32-bit DMACR defines the basic operating configuration of the DMA.
The DMA arbitrates channel service requests in groups of 16 channels. The 64- and 32-channel
configurations have four groups (3,2,1,0) and two groups (1,0), respectively; the 16 channel configuration
has only one group (0). Group 3 contains channels 63-48, group 2 contains channels 47-32, group 1
contains channels 31-16, and group 0 contains channels 15-0.
Arbitration within a group can be configured to use either a fixed-priority or a round-robin selection. In
fixed-priority arbitration, the highest priority channel requesting service is selected to execute. The
priorities are assigned by the channel priority registers (see
Section 15.3.1.17, DMA Channel n Priority
(DCHPRIn), n = 0,..., {15,31,63} registers). In round-robin arbitration mode, the channel priorities are
ignored and the channels within each group are cycled through without regard to priority.
The group priorities operate in a similar fashion. In group fixed-priority arbitration mode, channel service
requests in the highest priority group are executed first where priority level 3 is the highest and priority
level 0 is the lowest. The group priorities are assigned in the GRPnPri registers. All group priorities must
have unique values prior to any channel service requests occur, otherwise a configuration error will be
reported. Unused group priority registers, per configuration, are unimplemented in the DMACR. In group
round-robin mode, the group priorities are ignored and the groups are cycled through without regard to
priority.
0x0124 DMA Channel 36
Priority (DCHPRI36)
DMA Channel 37
Priority (DCHPRI37)
DMA Channel 38
Priority (DCHPRI38)
DMA Channel 39
Priority (DCHPRI39)
0x0128 DMA Channel 40
Priority (DCHPRI40)
DMA Channel 41
Priority (DCHPRI41)
DMA Channel 42
Priority (DCHPRI42)
DMA Channel 43
Priority (DCHPRI43)
0x012C DMA Channel 44
Priority (DCHPRI44)
DMA Channel 45
Priority (DCHPRI45)
DMA Channel 46
Priority (DCHPRI46)
DMA Channel 47
Priority (DCHPRI47)
0x0130 DMA Channel 48
Priority (DCHPRI48)
DMA Channel 49
Priority (DCHPRI49)
DMA Channel 50
Priority (DCHPRI50)
DMA Channel 51
Priority (DCHPRI51)
0x0134 DMA Channel 52
Priority (DCHPRI52)
DMA Channel 53
Priority (DCHPRI53)
DMA Channel 54
Priority (DCHPRI54)
DMA Channel 55
Priority (DCHPRI55)
0x0138 DMA Channel 56
Priority (DCHPRI56)
DMA Channel 57
Priority (DCHPRI57)
DMA Channel 58
Priority (DCHPRI58)
DMA Channel 59
Priority (DCHPRI59)
0x013C DMA Channel 60
Priority (DCHPRI60)
DMA Channel 61
Priority (DCHPRI61)
DMA Channel 62
Priority (DCHPRI62)
DMA Channel 63
Priority (DCHPRI63)
0x0140–0x0FFC Reserved
0x1000–0x11FC TCD00-TCD15
0x1200–0x13FC TCD16-TCD31
0x1400–0x15FC TCD32-TCD47
0x1600–0x17FC TCD48-TCD63
Table 15-1. DMA 32-bit memory map (continued)
DMA Offset Register
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