Enhanced Direct Memory Access (eDMA)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 479
Minor loop offsets are address offset values added to the final source address (saddr) or destination address
(daddr) upon minor loop completion. When minor loop offsets are enabled, the minor loop offset (mloff)
is added to the final source address (saddr), or the final destination address (daddr), or both prior to the
addresses being written back into the TCD. If the major loop is complete, the minor loop offset is ignored
and the major loop address offsets (slast and dlast_sga) are used to compute the next saddr and daddr
values.
When minor loop mapping is enabled (DMACR[EMLM] = 1), TCDn word2 is redefined. A portion of
TCDn word2 is used to specify multiple fields: an source enable bit (smloe) to specify the minor loop offset
should be applied to the source address (saddr) upon minor loop completion, an destination enable bit
(dmloe) to specify the minor loop offset should be applied to the destination address (daddr) upon minor
loop completion, and the sign extended minor loop offset value (mloff). The same offset value (mloff) is
used for both source and destination minor loop offsets. When either minor loop offset is enabled (smloe
set or dmloe set), the nbytes field is reduced to 10 bits. When both minor loop offsets are disabled (smloe
cleared and dmloe cleared), the nbytes field is a 30-bit vector.
When minor loop mapping is disabled (DMACR[EMLM] = 0), all 32 bits of TCDn word2 are assigned to
the nbytes field. See Section 15.3.1.18, Transfer Control Descriptor (TCD), for more details.
See Figure 15-2 and Table 15-2 for the DMACR definition.
Address: Base + 0x0000 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CX ECX
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
GRP3PRI GRP2PRI GRP1PRI GRP0PRI
EML
M
CLM HALT HOE
ERG
A
ERC
A
EDB
G
EBW
W
Reset 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0
Figure 15-2. DMA Control Register (DMACR)
Table 15-2. DMA Control Register (DMACR) field descriptions
Field Description
CX Cancel Transfer
0 Normal operation.
1 Cancel the remaining data transfer. Stop the executing channel and force the minor loop to
be finished. The cancel takes effect after the last write of the current read/write sequence.
The CXFR bit clears itself after the cancel has been honored. This cancel retires the channel
normally as if the minor loop was completed.
ECX Error Cancel Transfer
0 Normal operation.
1 Cancel the remaining data transfer in the same fashion as the CX cancel transfer. Stop the
executing channel and force the minor loop to be finished. The cancel takes effect after the
last write of the current read/write sequence. The ECX bit clears itself after the cancel has
been honored. In addition to cancelling the transfer, the ECX treats the cancel as an error
condition; thus updating the DMAES register and generating an optional error interrupt (see
Section 15.3.1.2, DMA Error Status (DMAES) register).
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