Enhanced Direct Memory Access (eDMA)
MPC5606S Microcontroller Reference Manual, Rev. 7
480 Freescale Semiconductor
GRP3PRI Channel Group 3 Priority
Group 3 priority level when fixed priority group arbitration is enabled.
GRP2PRI Channel Group 2 Priority
Group 2 priority level when fixed priority group arbitration is enabled.
GRP1PRI Channel Group 1 Priority
Group 1 priority level when fixed priority group arbitration is enabled.
GRP0PRI Channel Group 0 Priority
Group 0 priority level when fixed priority group arbitration is enabled.
EMLM Enable Minor Loop Mapping
0 Minor loop mapping disabled. TCDn.word2 is defined as a 32-bit nbytes field.
1 Minor loop mapping enabled. When set,
TCDn.word2 is redefined to include individual enable fields, an offset field and the nbytes
field. The individual enable fields allow the minor loop offset to be applied to the source
address, the destination address, or both. The nbytes field is reduced when either offset is
enabled.
CLM Continuous Link Mode
0 A minor loop channel link made to itself will go through channel arbitration before being
activated again.
1 A minor loop channel link made to itself will not go through channel arbitration before being
activated again. Upon minor loop completion the channel will active again if that channel has
a minor loop channel link enabled and the link channel is itself. This effectively applies the
minor loop offsets and restarts the next minor loop.
HALT Halt DMA Operations
0 Normal operation.
1 Stall the start of any new channels. Executing channels are allowed to complete. Channel
execution will resume when the HALT bit is cleared.
HOE Halt On Error
0 Normal operation.
1 Any error will cause the HALT bit to be set. Subsequently, all service requests will be ignored
until the HALT bit is cleared.
ERGA Enable Round Robin Group Arbitration
0 Fixed priority arbitration is used for selection among the groups.
1 Round robin arbitration is used for selection among the groups.
ERCA Enable Round Robin Channel Arbitration
0 Fixed priority arbitration is used for channel selection within each group.
1 Round robin arbitration is used for channel selection within each group.
EDBG Enable Debug
0 The assertion of the ipg_debug input is ignored.
1 The assertion of the ipg_debug input causes the DMA to stall the start of a new channel.
Executing channels are allowed to complete. Channel execution will resume when either the
ipg_debug input is negated or the EDBG bit is cleared.
EBW Enable Buffered Writes
0 The bufferable write signal (hprot[2]) is not asserted during AMBA AHB writes.
1 The bufferable write signal (hprot[2]) is asserted on all AMBA AHB writes except for the last
write sequence.
Table 15-2. DMA Control Register (DMACR) field descriptions
Field Description
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