System Timer Module (STM)
MPC5606S Microcontroller Reference Manual, Rev. 7
1222 Freescale Semiconductor
39.3.2 Register descriptions
The following sections detail the individual registers within the STM programming model.
39.3.2.1 STM Control Register (STM_CR)
The STM Control Register (STM_CR) includes the prescale value, freeze control and timer enable bits.
Table 39-1. STM memory map
Address
Offset
Register Name Register description
Size
(bits)
Access Location
0x0000 STM_CR STM Control Register 32 R/W on page 1222
0x0004 STM_CNT STM Counter Value 32 R/W on page 1223
0x0008 Reserved
0x000C Reserved
0x0010 STM_CCR0 STM Channel 0 Control Register 32 R/W on page 1224
0x0014 STM_CIR0 STM Channel 0 Interrupt Register 32 R/W on page 1224
0x0018 STM_CMP0 STM Channel 0 Compare Register 32 R/W on page 1225
0x001C Reserved
0x0020 STM_CCR1 STM Channel 1 Control Register 32 R/W on page 1224
0x0024 STM_CIR1 STM Channel 1 Interrupt Register 32 R/W on page 1224
0x0028 STM_CMP1 STM Channel 1 Compare Register 32 R/W on page 1225
0x002C Reserved
0x0030 STM_CCR2 STM Channel 2 Control Register 32 R/W on page 1224
0x0034 STM_CIR2 STM Channel 2 Interrupt Register 32 R/W on page 1224
0x0038 STM_CMP2 STM Channel 2 Compare Register 32 R/W on page 1225
0x003C Reserved
0x0040 STM_CCR3 STM Channel 3 Control Register 32 R/W on page 1224
0x0044 STM_CIR3 STM Channel 3 Interrupt Register 32 R/W on page 1224
0x0048 STM_CMP3 STM Channel 3 Compare Register 32 R/W on page 1225
0x004C -
0x3FFF
Reserved
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