NXP Semiconductors MPC5606S - Transfer Control Descriptor (TCD)

Enhanced Direct Memory Access (eDMA)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 495
15.3.1.18 Transfer Control Descriptor (TCD)
Each channel requires a 32-byte transfer control descriptor for defining the desired data movement
operation. The TCD structure was previously discussed in detail in Section 15.2.2, Features. The channel
descriptors are stored in the local memory in sequential order: channel 0, channel 1, ... channel [n-1]. The
definitions of the TCD are presented as eight 32-bit values. Table 15-19 is a 32-bit view of the basic TCD
structure.
Figure 15-24 and Table define word 0 of the TCDn structure, the saddr field.
Address: Base + 0x0100 + n Access: User read/write
0 1 2 3 4 5 6 7
R
ECP DPA
GRPPRI[0:1]
CHPRI[0:3]
W
Reset 0 0 —
1
1
Defaults to channel n after reset.
—
1
—
1
—
1
—
1
—
1
Figure 15-23. DMA Channel n Priority (DCHPRIn) register
Table 15-18. DMA Channel n Priority (DCHPRIn) field descriptions
Name Description
ECP Enable Channel Preemption
0 Channel n cannot be suspended by a higher priority channel’s service request.
1 Channel n can be temporarily suspended by the service request of a higher priority channel.
DPA Disable Preempt Ability
0 Channel n can suspend a lower priority channel.
1 Channel n cannot suspend any channel, regardless of channel priority.
GRPPRI[0:1] Channel n Current Group Priority
Group priority assigned to this channel group when fixed-priority arbitration is enabled. These
two bits are read only; writes are ignored.
CHPRI[0:3] Channel n Arbitration Priority
Channel priority when fixed-priority arbitration is enabled.
Table 15-19. TCDn 32-bit memory structure
DMA Offset TCDn Field
0x1000 + (32 x n) + 0x00 Source Address (saddr)
0x1000 + (32 x n) + 0x04 Transfer Attributes
(smod, ssize, dmod, dsize)
Signed Source Address Offset (soff)
0x1000 + (32 x n) + 0x08 Signed Minor Loop Offset (smloe, dmloe, mloff) Inner “Minor” Byte
Count (nbytes)
0x1000 + (32 x n) + 0x0C Last Source Address Adjustment (slast)
0x1000 + (32 x n) + 0x10 Destination Address (daddr)
0x1000 + (32 x n) + 0x14 Current “Major” Iteration Count (citer) Signed Destination Address Offset (doff)
0x1000 + (32 x n) + 0x18 Last Destination Address Adjustment/Scatter Gather Address (dlast_sga)
0x1000 + (32 x n) + 0x1C Beginning “Major” Iteration Count (biter) Channel Control/Status
(bwc, major.linkch, done, active,
major.e_link, e_sg, d_req, int_half, int_maj,
start)