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NXP Semiconductors MPC5606S - Page 498

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Enhanced Direct Memory Access (eDMA)
MPC5606S Microcontroller Reference Manual, Rev. 7
496 Freescale Semiconductor
Figure 15-25. TCDn Word 0 (TCDn.saddr) field
Figure 15-26 and Table 15-21 define word 1 of the TCDn structure, the soff and transfer attribute fields.
Address: DMA_Offset + 0x1000 + (32 × n) + 0x00 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
saddr[0:15]
W
Reset
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
saddr[16:31]
W
Reset
Figure 15-24. TCDn Word 0 (TCDn.saddr) field
Table 15-20. TCDn Word 0 (TCDn.saddr) field description
Name Description
saddr[0:31] Source address
Memory address pointing to the source data.
Address: DMA_Offset + 0x1000 + (32 × n) + 0x04 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
smod[0:4] ssize[0:2] dmod[0:4] dsize[0:2]
W
Reset
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
soff[16:31]
W
Reset
Figure 15-26. TCDn Word 1 (TCDn.{soff,smod,ssize,dmod,dsize}) fields
Table 15-21. TCDn Word 1 (TCDn.{smod,ssize,dmod,dsize,soff}) field descriptions
Name Description
smod[0:4] Source address modulo
0 Source address modulo feature is disabled.
non-0 The value defines a specific address bit which is selected to be either the value after
saddr + soff calculation is performed or the original register value. This feature provides the
ability to easily implement a circular data queue. For data queues requiring power-of-2
“size” bytes, the queue should be based at a 0-modulo-size address and the smod field set
to the appropriate value to freeze the upper address bits. The bit select is defined as ((1 <<
smod[4:0])
1) where a resulting 1 in a bit location selects the next state address for the
corresponding address bit location and a 0 selects the original register value for the
corresponding address bit location. For this application, the soff is typically set to the
transfer size to implement post-increment addressing with the smod function constraining
the addresses to a 0-modulo-size range.

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