Flash Memory
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 641
For additional information on the address-based read access timing for emulation of other memory types,
see Section 17.4.4.12, Wait-State emulation.
Next, consider the memory map associated with the control and configuration registers.
There are multiple registers that control operation of the PFLASH2P_LCA. These registers are generically
defined as “Bus Interface Unit n (BIU n) Register” in the flash array documentation, where n = 0,1,2,3 and
are to be only referenced with 32-bit accesses. Note the first two flash array registers (BIU0, BIU1) are
reset to an SoC-defined value, while the remaining two array registers (BIU2, BIU3) are loaded at reset
from specific locations in the array’s shadow region.
Regardless of the number of populated banks or the number of flash arrays included in a given bank, the
configuration of the PFLASH2P_LCA is wholly specified by the BIU registers associated with bank0
array0. These register settings define the operating behavior of all flash banks; it is recommended that the
BIU registers for all physically present arrays be set to the bank0 array0 values.
NOTE
To perform program and erase operations, the control registers in the actual
referenced flash array must be programmed, but the configuration of the
PFLASH2P_LCA module is defined by the BIUn registers of bank0 array0.
The 32-bit memory map for the PFLASH2P_LCA control registers is shown in Table 17-63.
17.4.3.2 Register descriptions
This section details the individual registers of the PFLASH2P_LCA. To be consistent with the flash
documentation, this description uses a LSB=0 vector bit numbering convention.
0xFFEB_4000 0xFFEB_7FFF 16 Reserved for Code flash array 2 configuration
2
0xFFEB_8000 0xFFEB_BFFF 16 Reserved for Code flash array 3 configuration
2
1 This region is also aliased to address 0xC3F8_nnnn.
2 This region is also aliased to address 0xC3FB_nnnn.
Table 17-63. PFLASH2P_LCA 32-bit memory map
Address Register
Acces
s
Reset Value Location
0xFFE8_8000
+ 0x01C
Platform Flash Configuration Register 0 (PFCR0) R/W 0x1085_93ED on page 642
0xFFE8_8000
+ 0x020
Platform Flash Configuration Register 1 (PFCR1) R/W 0x1085_8181 on page 646
0xFFE8_8000
+
0x024
Platform Flash Access Protection Register (PFAPR) R/W 0xFFFF_FFF
F
on page 647
Table 17-62. PFLASH2P_LCA decodes for flash-related regions in the system memory map (continued)
Start Address End Address Size [KB] Region
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