Flash Memory
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 647
17.4.3.2.3 Platform Flash Access Protection Register (PFAPR)
The PFLASH Access Protection Register (PFAPR) is used to control read and write accesses to the flash
based on system master number. Prefetching capabilities are defined on a per master basis. This register
also defines the arbitration mode between the 2 AHB ports for the PFLASH2P_LCA. The register is
described below in Figure 17-46 and Table 17-66.
B1_RWSC Bank1 Read Wait State Control. This field is used to control the number of wait-states to be added
to the flash array access time for reads. This field must be set to a value corresponding to the
operating frequency of the PFLASH and the actual read access time of the PFLASH. The required
settings are documented in the SoC specification. Higher operating frequencies require non-zero
settings for this field for proper flash operation.
Shown below are the maximum operating frequencies for legal APC and RWSC settings based on
estimated low-cost flash access times at 150C. The integrator is strongly encouraged to verify these
settings based on actual silicon results.
0 MHz,< 23 MHz APC=RWSC=0
23 MHz,< 45 MHz APC=RWSC=1
45 MHz,< 68 MHz APC=RWSC=2
68 MHz,< 90 MHz APC=RWSC=3
00000 No additional wait-states are added
00001 1 additional wait-state is added
00010 2 additional wait-states are added
...
111111 31 additional wait-states are added
This field is ignored in single bank flash configurations.
This field is set to 0b00010 by hardware reset.
B1_RWWC Bank1 Read-While-Write Control. This 3-bit field defines the controller response to flash reads while
the array is busy with a program (write) or erase operation.
0-- Terminate any attempted read while write/erase with an error response
111 Generate a bus stall for a read while write/erase, disable the stall notification interrupt, disable
the abort + abort notification interrupt
110 Generate a bus stall for a read while write/erase, enable the stall notification interrupt, disable
the abort + abort notification interrupt
101 Generate a bus stall for a read while write/erase, enable the operation abort, disable the abort
notification interrupt
100 Generate a bus stall for a read while write/erase, enable the operation abort and the abort
notification interrupt
This field is set to 0b111 by hardware reset enabling the stall-while-write/erase and disabling the
abort and notification interrupts.
This field is ignored in single bank flash configurations.
B1_P1_BFE Bank1, Port 1 Buffer Enable. This bit enables or disables read hits from the 128-bit holding register.
It is also used to invalidate the contents of the holding register. This bit is set by hardware reset,
enabling the use of the holding register.
0 The holding register is disabled from satisfying read requests.
1 The holding register is enabled to satisfy read requests on hits.
B1_P0_BFE Bank1, Port 0 Buffer Enable. This bit enables or disables read hits from the 128-bit holding register.
It is also used to invalidate the contents of the holding register. This bit is set by hardware reset,
enabling the use of the holding register.
0 The holding register is disabled from satisfying read requests.
1 The holding register is enabled to satisfy read requests on hits.
Table 17-65. PFLASH Configuration Register 1 field descriptions (continued)
Field Description
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