NXP Semiconductors MPC5606S - SPI Mode Interrupt and DMA Requests

Quad Serial Peripheral Interface (QuadSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
1046 Freescale Semiconductor
• Continuous SCK with CONT bit set and entering Stop mode or Module Disable mode.
Figure 30-34 shows timing diagram for Continuous SCK format with Continuous Selection enabled.
Figure 30-34. Continuous SCK timing diagram (CONT=1)
30.5.2.10 SPI mode interrupt and DMA requests
In both SPI modes the QuadSPI has four conditions that can only generate interrupt requests and two
conditions that can generate interrupt or DMA request alternatively. Table 30-44 lists the six conditions.
Note that the flags mentioned in the table relate to the SPI status register QSPI_SPISR
Each condition has a flag bit in the SPI Status Register (QSPI_SPISR) and a Request Enable bit in the SPI
Interrupt and DMA Request Select and Enable Register (QSPI_SPIRSER). The TX FIFO Fill Flag
(TFFF) and RX FIFO Drain Flag (RFDF) generate interrupt requests or DMA requests depending on the
TFFF_DIRS and RFDF_DIRS bits in the QSPI_SPIRSER.
30.5.2.10.1 End of Queue Interrupt Request
The End of Queue Request indicates that the end of a transmit queue is reached. The End of Queue Request
is generated when the EOQ bit in the executing SPI Command is asserted and the EOQF_RE bit in the
QSPI_SPIRSER is asserted.
Table 30-44. SPI mode interrupt and DMA request conditions
Condition
Flag
(QSPI_SPISR)
Interrupt DMA
End of Queue (EOQ) EOQF X
TX FIFO Fill TFFF X X
Transfer Complete TCF X
TX FIFO Underrun TFUF X
RX FIFO Drain RFDF X X
RX FIFO Overflow RFOF X
SCK
PCS
SCK
Master SO
Master SI
(CPOL = 0)
(CPOL = 1)
transfer 1 transfer 2