NXP Semiconductors MPC5606S - Low-Power Peripheral Configuration Registers (ME_LP_PC0...7)

Mode Entry Module (MC_ME)
MPC5606S Microcontroller Reference Manual, Rev. 7
932 Freescale Semiconductor
25.3.2.21 Low-Power Peripheral Configuration Registers (ME_LP_PC0…7)
These registers configure eight different types of peripheral behavior during non-run modes.
SAFE Peripheral control during Safe
0 Peripheral is frozen with clock gated
1 Peripheral is active
TEST Peripheral control during Test
0 Peripheral is frozen with clock gated
1 Peripheral is active
RESET Peripheral control during Reset
0 Peripheral is frozen with clock gated
1 Peripheral is active
Address 0xC3FD_C0A0–0xC3FD_C0BC Access: Supervisor read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0
STANDBY
0 0
STOP
0
HALT
0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 25-22. Low-Power Peripheral Configuration Registers (ME_LP_PC0…7)
Table 25-14. Low-Power Peripheral Configuration Registers (ME_LP_PC0…7) field descriptions
Field Description
STANDBY Peripheral control during Standby
0 Peripheral is frozen with clock gated
1 Peripheral is active
STOP Peripheral control during Stop
0 Peripheral is frozen with clock gated
1 Peripheral is active
HALT Peripheral control during Halt
0 Peripheral is frozen with clock gated
1 Peripheral is active
Table 25-13. Run Peripheral Configuration Registers (ME_RUN_PC0…7) field descriptions (continued)
Field Description