NXP Semiconductors MPC5606S - DMA Enable Request (DMAERQH, DMAERQL) Registers

Enhanced Direct Memory Access (eDMA)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 483
15.3.1.3 DMA Enable Request (DMAERQH, DMAERQL) registers
The DMAERQ{H,L} registers provide a bit map for the implemented channels {16,32,64} to enable the
request signal for each channel. DMAERQH supports channels 63-32, while DMAEQRL covers channels
31-00. The state of any given channel enable is directly affected by writes to this register; it is also affected
by writes to the DMASERQ and DMACERQ registers. The DMA{S,C}ERQ registers are provided so that
the request enable for a single channel can easily be modified without the need to perform a
read-modify-write sequence to the DMAERQ{H,L} registers.
Both the DMA request input signal and this enable request flag must be asserted before a channel’s
hardware service request is accepted. The state of the DMA enable request flag does not affect a channel
service request made explicitly through software or a linked channel request. See Figure 15-4, Figure 15-5,
and Table 15-4 for the DMAERQ definition.
DOE Destination Offset Error
0 No destination offset configuration error.
1 The last recorded error was a configuration error detected in the TCD.doff field. TCD.doff is
inconsistent with TCD.dsize.
NCE Nbytes/Citer Configuration Error
0 No nbytes/citer configuration error.
1 The last recorded error was a configuration error detected in the TCD.nbytes or TCD.citer fields.
TCD.nbytes is not a multiple of TCD.ssize and TCD.dsize, or TCD.citer is equal to zero, or
TCD.citer.e_link is not equal to TCD.biter.e_link.
SGE Scatter/Gather Configuration Error
0 No scatter/gather configuration error.
1 The last recorded error was a configuration error detected in the TCD.dlast_sga field. This field
is checked at the beginning of a scatter/gather operation after major loop completion if
TCD.e_sg is enabled. TCD.dlast_sga is not on a 32-byte boundary.
SBE Source Bus Error
0 No source bus error.
1 The last recorded error was a bus error on a source read.
DBE Destination Bus Error
0 No destination bus error.
1 The last recorded error was a bus error on a destination write.
Address: Base + 0x0008 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
ERQ
63
ERQ
62
ERQ
61
ERQ
60
ERQ
59
ERQ
58
ERQ
57
ERQ
56
ERQ
55
ERQ
54
ERQ
53
ERQ
52
ERQ
51
ERQ
50
ERQ
49
ERQ
48
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
ERQ
47
ERQ
46
ERQ
45
ERQ
44
ERQ
43
ERQ
42
ERQ
41
ERQ
40
ERQ
39
ERQ
38
ERQ
37
ERQ
36
ERQ
35
ERQ
34
ERQ
33
ERQ
32
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 15-4. DMA Enable Request High (DMAERQH) register
Table 15-3. DMA Error Status (DMAES) field descriptions (continued)
Name Description