Flash Memory
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 573
NOTE
On this device, BIU2 and PFAPR are the same register. Your software may
refer to either register. For clarity, however, it is recommended that you use
PFAPR.
17.2.6.15 User Test 0 register (UT0)
The User Test feature gives the user of the flash module the ability to perform test features on the flash
memory. The User Test 0 Register allows to control the way in which the flash memory content check is
done.
Bits MRE, MRV, AIS, EIE and DSI7-0 of the User Test 0 Register are not accessible whenever
MCR.DONE or UT0.AID are low: reading returns indeterminate data while writing has no effect.
Table 17-22. BIU2 field descriptions
Field Description
0:31 BI231-00: Bus Interface unit 2 31-00 (Read/Write)
The BI231-00 generic registers are reset based on the information stored in NVBIU2.
The writability of the bits in this register can be locked.
The use of this bus is SoC specific.
Address Offset: 0x0003C Reset value: 0x00000001
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
UTE 0 0 0 0 0 0 0 DSI7 DSI6 DSI5 DSI4 DSI3 DSI2 DSI1 DSI0
rw/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0 0 0 0 0 0 0 0 0 X MRE MRV EIE AIS AIE AID
r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 r/1
Figure 17-13. User Test 0 register (UT0)
Table 17-23. UT0 field descriptions
Field Description
0 UTE: User Test Enable (Read/Clear)
This status bit gives indication when User Test is enabled. All bits in UT0-2 and UMISR0-4 are locked when
this bit is 0.
This bit is not writeable to a 1, but may be cleared. The reset value is 0.
The method to set this bit is to provide a password, and if the password matches, the UTE bit is set to
reflect the status of enabled, and is enabled until it is cleared by a register write.
For UTE the password 0xF9F99999 must be written to the UT0 register.
1:7 Reserved (Read Only).
Write these bits has no effect and read these bits always outputs 0.