Deserial Serial Peripheral Interface (DSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
286 Freescale Semiconductor
11.3 Overview
The register content is transmitted using an SPI protocol. There are two identical DSPI modules (DSPI 0
and DSPI 1) on the device.
For queued operations the SPI queues reside in internal SRAM which is external to the DSPI. Data
transfers between the queues and the DSPI FIFOs are accomplished through the use of the eDMA
controller or through host software.
Figure 11-2 shows a DSPI with external queues in internal SRAM.
Figure 11-2. DSPI with queues and eDMA
11.4 Features
The DSPI supports these SPI features:
• Full-duplex, three-wire synchronous transfers
• Master and Slave mode
• Buffered transmit and receive operation using the TX and RX FIFOs, with depths of five entries
• Visibility into TX and RX FIFOs for ease of debugging
• FIFO bypass mode for low-latency updates to SPI queues
Internal SRAM
TX queue
RX queue
Address/control
TX FIFO
DSPI
RX FIFO
RX data
TX data
TX data RX data
Shift register
eDMA controller
Address/control
or host CPU
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