System Integration Unit Lite (SIUL)
MPC5606S Microcontroller Reference Manual, Rev. 7
1210 Freescale Semiconductor
Figure 37-21. External interrupt pad diagram
1
This value is valid in the 176-pin LQFP and the 208-pin packages
37.6.4.1 External interrupt management
Each interrupt can be enabled or disabled independently. This can be performed using the Interrupt
Request Enable Register (see Section 37.5.3.4, Interrupt Request Enable Register (IRER)). A pad defined
as an external interrupt can be configured to recognize interrupts with an active rising edge, an active
falling edge or both edges being active. A setting of having both edge events disabled is reserved and
should not be configured. External interrupts require that the associated input buffer for the pad is enabled
(PCR[IBE]=1).
The active EIRQ edge is controlled through the configuration of the registers IREER and IFEER.
Each external interrupt supports an individual flag which is held in the Flag register (see Section 37.5.3.3,
Interrupt Status Flag Register (ISR)). This register is a clear-by-write-1 register type, preventing
inadvertent overwriting of other flags in the same register. The external interrupt flags map to the INTC
vector table as follows:
• EIF[7:0] map to the External IRQ_0 vector
• EIF[13:8] map to the External IRQ_1 vector
37.7 Pin muxing
For pin muxing, please see Chapter 3, Signal Description, of this document.
Interrupt
Controller
Int
Vectors
EIF[13:8]
1
EIF[7:0]
IRE[13:0]
1
Pads
IREE[13:0]
1
Interrupt Edge Enable
IFEE[13:0]
1
Falling
Rising
Edge Detection
Glitch Filter
IFE[13:0]
1
MAXCOUNT[x]
IRQ Glitch Filter enable
Glitch filter Counter_n
IFCP[3:0]
Glitch filter Prescaler
Interrupt enable
OR OR
External IRQ_1
1
External IRQ_0
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