NXP Semiconductors MPC5606S - Functional Description

Periodic Interrupt Timer (PIT)
MPC5606S Microcontroller Reference Manual, Rev. 7
978 Freescale Semiconductor
27.4 Functional description
27.4.1 General
This section gives detailed information on the internal operation of the module. Each timer can be used to
generate trigger pulses as well as to generate interrupts, each interrupt will be available on a separate
interrupt line.
27.4.1.1 Timers
The timers generate triggers at periodic intervals, when enabled. They load their start values, as specified
in their LDVAL registers, then count down until they reach 0. Then they load their respective start value
again. Each time a timer reaches 0, it will generate a trigger pulse, and set the interrupt flag.
All interrupts can be enabled or masked (by setting the TIE bits in the TCTRL registers). A new interrupt
can be generated only after the previous one is cleared.
If desired, the current counter value of the timer can be read via the CVAL registers.
The counter period can be restarted, by first disabling, then enabling the timer with the TEN bit (see
Figure 27-7).
The counter period of a running timer can be modified, by first disabling the timer, setting a new load value
and then enabling the timer again (see
Figure 27-8).
It is also possible to change the counter period without restarting the timer by writing the LDVAL register
with the new load value. This value will then be loaded after the next trigger event (see Figure 27-9).
Offset: Channel_base + 0x0C Access: Read/Write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIF
W w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 27-6. Timer Flag (TFLG) register
Table 27-7. TFLG field descriptions
Field Description
TIF Time Interrupt Flag. TIF is set to 1 at the end of the timer period.This flag can be cleared only by
writing it with a 1. Writing a 0 has no effect. If enabled (TIE = 1), TIF causes an interrupt request.
0 Timeout has not yet occurred
1 Timeout has occurred