NXP Semiconductors MPC5606S - Functional Description

Enhanced Direct Memory Access (eDMA)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 505
15.4 Functional description
This section provides an overview of the microarchitecture and functional operation of the DMA module.
15.4.1 DMA microarchitecture
The DMA module is partitioned into two major modules: the DMA engine and the transfer control
descriptor local memory. Additionally, the DMA engine is further partitioned into four submodules, which
are detailed below.
• DMA engine
— addr_path: This module implements registered versions of two channel transfer control
descriptors: channel “x” and channel “y,” and is responsible for all the master bus address
calculations. All the implemented channels provide the exact same functionality. This
hardware structure allows the data transfers associated with one channel to be preempted after
the completion of a read/write sequence if a higher priority channel service request is asserted
while the first channel is active. Once a channel is activated, it runs until the minor loop is
completed unless preempted by a higher priority channel. This capability provides a
mechanism (optionally enabled by DCHPRIn[ECP]) where a large data move operation can be
preempted to minimize the time another channel is blocked from execution.
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When any other channel is activated, the contents of its transfer control descriptor is read from
the local memory and loaded into the registers of the other addr_path.channel_{x,y}. Once the
inner minor loop completes execution, the addr_path hardware writes the new values for the
int_half Enable an interrupt when major counter is half complete
If this flag is set, the channel generates an interrupt request by setting the appropriate bit in the
DMAINT register when the current major iteration count reaches the halfway point. Specifically,
the comparison performed by the DMA engine is (citer
= (biter >> 1)). This halfway point
interrupt request is provided to support double-buffered schemes or other types of data
movement where the processor needs an early indication of the transfer’s progress. The
halfway complete interrupt is disabled when biter values are less than two.
0 The half-point interrupt is disabled.
1 The half-point interrupt is enabled.
int_maj Enable an interrupt when major iteration count completes
If this flag is set, the channel generates an interrupt request by setting the appropriate bit in the
DMAINT register when the current major iteration count reaches zero.
0 The end-of-major loop interrupt is disabled.
1 The end-of-major loop interrupt is enabled.
start Channel start
If this flag is set, the channel is requesting service. The DMA hardware automatically clears this
flag after the channel begins execution.
0 The channel is not explicitly started.
1 The channel is explicitly started via a software initiated service request.
Table 15-28. TCDn Word 7 (TCDn.{biter, control/status}) field descriptions (continued)
Name Description