Clock Description
MPC5606S Microcontroller Reference Manual, Rev. 7
216 Freescale Semiconductor
8.9.2 Overview
The FMPLLs enable the user to generate high-speed system clocks from a common 4 MHz to 16 MHz
input clock. Further, the FMPLLs support programmable frequency modulation of the system clock. The
PLL multiplication factor and the output clock divider ratio are both software-configurable.
NOTE
The user must take care not to program the device with a frequency higher
than allowed (no hardware check is provided).
The FMPLL block diagram is shown in Figure 8-23.
Figure 8-23. FMPLL block diagram
8.9.3 Features
Each FMPLL has the following major features:
• Input clock frequency from 4 MHz to 16 MHz
• Voltage controlled oscillator (VCO) range from 256 MHz to 512 MHz
• Reduced frequency divider (RFD) for reduced frequency operation without forcing the PLL to
relock
• Frequency-modulated PLL
— Modulation enabled/disabled through software
— Triangle wave modulation
• Programmable modulation depth
— ±0.25% to ±4% deviation from center-spread frequency
— –0.5% to +8% deviation from down-spread frequency
— Programmable modulation frequency dependent on reference frequency
• Self-clocked mode (SCM) operation
• Five available modes
— Normal mode
— Progressive clock switching
— Normal mode with FM
— Power-down mode
— 1:1 mode (FMPLL0 only)
BUFFER
Charge
pump
low pass
filter
VCO
IDF
DIV2
NDIV
loop
frequency
divider
FXOSC
MODE
ODF
DIV4
MODE
PHI
To Next Page
Loading...
