Clock Description
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 189
• Auxiliary Clock 0: Display Control Unit (DCU)
• Auxiliary Clock 1: eMIOS_1
• Auxiliary Clock 2: eMIOS_0
• Auxiliary Clock 3: QuadSPI (uses undivided system clock when in DSPI mode)
8.3 Clock gating
The MPC5606S provides the user with the possibility of gating the clock to certain peripherals. See
Section 25.4.6, Peripheral clock gating, for details.
Peripherals sets 1, 2, and 3, and the DCU, eMIOS, and QuadSPI peripherals can be configured to use
specific clocks. In the case of peripheral sets 1, 2, and 3, the choice of clock is limited to the system clock
optionally divided by up to 16. See Section 8.4.3.1.4, System Clock Divider Configuration Registers
(CGM_SC_DC0…2). In the case of the DCU, eMIOS_0, eMIOS_1, and QuadSPI peripherals there is a
choice of source clocks. For the eMIOS0 and eMIOS1 peripherals there is the option to further divide the
chosen clock. See Section 8.4.4.2, Auxiliary clock generation.
Table 8-1 shows the peripheral sets, their peripherals, and the associated registers to enable and generate
clocks to these peripherals. Peripherals not explicitly listed in a peripheral set or using an auxiliary clock
use the system clock (or where available an alternative chosen within the peripheral) as their reference.
Table 8-1. Peripheral clock generation registers
Peripheral set Peripherals
Registers to enable and
generate clock
1 LINFlex
I
2
C
SMC
SSD
SGL
LCD
CGM_SC_DC0
2 FlexCAN
CAN Sampler
DSPI
CGM_SC_DC1
3 ADC CGM_SC_DC2
— DCU CGM_AC0_SC
— eMIOS_0 CGM_AC1_SC
CGM_AC1_DC0
— eMIOS_1 CGM_AC2_SC
CGM_AC2_DC0
— QuadSPI CGM_AC3_SC
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