NXP Semiconductors MPC5606S - Memory Map;Register Definition

Enhanced Direct Memory Access (eDMA)
MPC5606S Microcontroller Reference Manual, Rev. 7
476 Freescale Semiconductor
/* since the major loop is complete, perform the final address adjustments */
/* sum the current {src,dst} addresses with “last” adjustment */
write_to_local_memory [channel].saddr = dma_engine.saddr + dma_engine.slast;
write_to_local_memory [channel].daddr = dma_engine.daddr + dma_engine.dlast;
/* restore the major iteration count to the beginning value */
write_to_local_memory [channel].citer = dma_engine.biter;
/* check for interrupt assertion at completion of the major iteration */
if (dma_engine.int_maj)
generate_interrupt (channel);
/* check if the ipd_req is to be disabled at completion of the major iteration */
if (dma_engine.d_req)
DMAERQ [channel] = 0;
/* check for a scatter/gather transfer control descriptor */
if (dma_engine.e_sg) {
/* load new transfer control descriptor from the address defined by dlast_sga */
write_to_local_memory [channel] =
read_from_amba-ahb(dma_engine.dlast_sga,32);
}
if (dma_engine.major.e_link)
TCD[major.linkch].start = 1; /* specified channel service req */
dma_engine.active = 0; /* clear the channel busy flag */
dma_engine.done = 1; /* set the channel done flag */
}
else { /* configuration error detected, abort the channel */
dma_engine.error_status = error_type; /* record the error */
dma_engine.active = 0; /* clear the channel busy flag */
/* check for interrupt assertion on error */
if (dma_engine.int_err)
generate_interrupt (channel);
}
For more details, consult Section 15.3.1, Register descriptions, and Section 15.4, Functional description.
15.3 Memory map/register definition
The DMA’s programming model is partitioned into two sections, both mapped into the slave bus space:
the first region defines a number of registers providing control functions, while the second region
corresponds to the local transfer control descriptor memory.
Reading an unimplemented register bit or memory location will return the value of zero. Write the value
of zero to unimplemented register bits. Any access to a reserved memory location will result in a bus error.
Reserved memory locations are indicated in the memory map. For 16- and 32-channel implementations,
reserved memory also includes the high order “H” registers containing channels 63–32 data (DMAERQH,
DMAEEIH, DMAINTH, and DMAERRH).
Many of the control registers have a bit width that matches the number of channels implemented in the
module; that is, 16, 32, or 64 bits in size. Registers associated with a 64-channel design are implemented
as two 32-bit registers, and include an “H” and “L” suffixes, signaling the “high” and “low” portions of