NXP Semiconductors MPC5606S - DMA Set Enable Request (DMASERQ) Register

Enhanced Direct Memory Access (eDMA)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 485
15.3.1.5 DMA Set Enable Request (DMASERQ) register
The DMASERQ register provides a simple memory-mapped mechanism to set a given bit in the
DMAERQ{H,L} registers to enable the DMA request for a given channel. The data value on a register
write causes the corresponding bit in the DMAERQ{H,L} register to be set. A data value of 64 to 127
(regardless of the number of implemented channels) provides a global set function, forcing the entire
contents of DMAERQ{H,L} to be asserted. If bit 0 (NOP) is set, the command is ignored. This allows
multiple byte registers to be written as a 32-bit word. Reads of this register return all zeroes. See
Figure 15-8 and Table 15-6 for the DMASERQ definition.
Address: Base + 0x0010 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
EEI
63
EEI
62
EEI
61
EEI
60
EEI
59
EEI
58
EEI
57
EEI
56
EEI
55
EEI
54
EEI
53
EEI
52
EEI
51
EEI
50
EEI
49
EEI
48
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
EEI
47
EEI
46
EEI
45
EEI
44
EEI
43
EEI
42
EEI
41
EEI
40
EEI
39
EEI
38
EEI
37
EEI
36
EEI
35
EEI
34
EEI
33
EEI
32
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 15-6. DMA Enable Error Interrupt High (DMAEEIH) register
Address: Base + 0x0014 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
EEI
31
EEI
30
EEI
29
EEI
28
EEI
27
EEI
26
EEI
25
EEI
24
EEI
23
EEI
22
EEI
21
EEI
20
EEI
19
EEI
18
EEI
17
EEI
16
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
EEI
15
EEI
14
EEI
13
EEI
12
EEI
11
EEI
10
EEI
09
EEI
08
EEI
07
EEI
06
EEI
05
EEI
04
EEI
03
EEI
02
EEI
01
EEI
00
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 15-7. DMA Enable Error Interrupt Low (DMAEEIL) Register
Table 15-5. DMA Enable Error Interrupt (DMAEEIH, DMAEEIL) field descriptions
Name Description
EEIn,
n = 0,... 15
n = 0,... 31
n = 0,... 63
Enable Error Interrupt n
0 The error signal for channel n does not generate an error interrupt.
1 The assertion of the error signal for channel n generate an error interrupt request.