Display Control Unit (DCU)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 371
Figure 12-20. Threshold Register
12.3.4.19 Interrupt Status Register (INT_STATUS)
Figure 12-21 indicates the interrupt status register. See Section 12.5.4, Interrupt generation, for a
description of how the DCU collects interrupt events into different source groups.
Offset: 0x1E8 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0
LS_BF_VS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
OUT_BUF_HIGH OUT_BUF_LOW
W
Reset 0 1 1 1 1 0 0 0 0 0 0 0 1 0 1 0
Table 12-22. Threshold Register field descriptions
Field Description
6–15
LS_BF_VS
Lines before VSYNC threshold value. The LS_BF_VS status flag (in INT_STATUS) is set this
number of lines before the VSYNC signal is asserted.
16–23
OUT_BUF_HIGH
Output buffer high threshold (in pixels). When the output buffer exceeds this value the datapath
clock is suspended.
24–31
OUT_BUF_LOW
Output buffer filling low Threshold (in pixels).This value is used to generate the underrun
exception (UNDRUN in INT_STATUS).
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