Analog-to-Digital Converter (ADC)
MPC5606S Microcontroller Reference Manual, Rev. 7
138 Freescale Semiconductor
The lower and higher threshold values for the analog watchdog are programmed using the registers
THRHLR.
For example, if channel number 3 is to be monitored with threshold values in THRHLR1, then the THRCH
field is programmed in the TRC1 register to select channel number 3.
A set of threshold registers (THRHLRx and TRCx) can be linked only to a single channel for a particular
THRCH value. If another channel is to be monitored with the same threshold values, then the THRCH field
in the TRCx register has to be programmed again.
NOTE
If the higher threshold for the analog watchdog is programmed lower than
the lower threshold and the converted value is less than the lower threshold,
then the WDGxL interrupt for the low threshold violation is set. Otherwise,
if the converted value is greater than the lower threshold (consequently also
greater than the higher threshold), then the interrupt WDGxH for high
threshold violation is set. Thus, the user should avoid that situation as it
could lead to misinterpretation of the watchdog interrupts.
5.3.5 DMA functionality
A DMA request can be programmed after the conversion of every channel by setting the respective
masking bit in the DMAR registers. The DMAR masking registers must be programmed before starting
any conversion. There is one DMAR per channel type.
The DMA transfers can be enabled using the DMAEN bit of DMAE register. When the DCLR bit of
DMAE register is set, then the DMA request is cleared on the reading of the register for which DMA
transfer has been enabled.
5.3.6 Interrupts
The ADC generates the following maskable interrupt signals:
• ADC_EOC interrupt requests
— EOC (end of conversion)
— ECH (end of chain)
— JEOC (end of injected conversion)
— JECH (end of injected chain)
• WDGxL and WDGxH (watchdog threshold) interrupt requests
Interrupts are generated during the conversion process to signal events such as End Of Conversion, as
explained in the register description for CEOCFR. Two 7-bit registers named CEOCFR (Channel Pending
Registers) and IMR (Interrupt Mask Register) are provided in order to check and enable the interrupt
request to EIC module.
Interrupts can be individually enabled on a channel-by-channel basis by programming the CIMR (Channel
Interrupt Mask Register).
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