NXP Semiconductors MPC5606S - DMA General Purpose Output Register (DMAGPOR) Register

Enhanced Direct Memory Access (eDMA)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 493
15.3.1.16 DMA General Purpose Output Register (DMAGPOR) register
The optional DMAGPOR register provides a general purpose register in the programmer’s model that
outputs the register contents. The DMAGPOR performs no functions within the DMA2. This general
purpose register is enabled when SPP_DMA2_ENABLE_GPOR is defined. This register may be used by
the SoC integrator to define and display configuration information.
See Figure 15-22 and Table 15-17 for the DMAGPOR definition.
Address: Base + 0x0030 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
HRS
63
HRS
62
HRS
61
HRS
60
HRS
59
HRS
58
HRS
57
HRS
56
HRS
55
HRS
54
HRS
53
HRS
52
HRS
51
HRS
50
HRS
49
HRS
48
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
HRS
47
HRS
46
HRS
45
HRS
44
HRS
43
HRS
42
HRS
41
HRS
40
HRS
39
HRS
38
HRS
37
HRS
36
HRS
35
HRS
34
HRS
33
HRS
32
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 15-20. DMA Hardware Request Status High (DMAHRSH) register
Address: Base + 0x0034 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
HRS
31
HRS
30
HRS
29
HRS
28
HRS
27
HRS
26
HRS
25
HRS
24
HRS
23
HRS
22
HRS
21
HRS
20
HRS
19
HRS
18
HRS
17
HRS
16
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
HRS
15
HRS
14
HRS
13
HRS
12
HRS
11
HRS
10
HRS
09
HRS
08
HRS
07
HRS
06
HRS
05
HRS
04
HRS
03
HRS
02
HRS
01
HRS
00
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 15-21. DMA Hardware Request Status Low (DMAHRSL) register
Table 15-16. DMA Hardware Request Status (DMAHRSH, DMAHRSL) field descriptions
Name Description
HRSn,
n = 0,... 15
n = 0,... 31
n = 0,... 63
DMA Hardware Request Status n
0 A hardware service request for channel n is not present.
1 A hardware service request for channel n is present.
Note: The hardware request status reflects the state of the request as seen by the
arbitration logic. Therefore, this status is affected by the DMAERQn bit.