Quad Serial Peripheral Interface (QuadSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
1038 Freescale Semiconductor
30.5.2.7.5 Peripheral Chip Select Strobe Enable (PCSS)
The PCSS signal provides a delay to allow the PCS signals to settle after a transition occurs thereby
avoiding glitches. When the QuadSPI is in Master mode and PCSSE bit is set in the QSPI_MCR, PCSS
provides a signal for an external demultiplexer to decode the PCS[4:0] and PCS[7:6] signals into as many
as 128 glitch-free PCS signals. Figure 30-26 shows the timing of the PCSS signal relative to PCS signals.
Figure 30-26. Peripheral Chip Select Strobe Timing
The delay between the assertion of the PCS signals and the assertion of PCSS is selected by the PCSSCK
field in the QSPI_CTAR based on the following formula:
Eqn. 30-5
At the end of the transfer the delay between PCSS negation and PCS negation is selected by the PASC field
in the QSPI_CTAR based on the following formula:
Eqn. 30-6
Table 30-42 shows an example of how to compute the t
pcssck
delay.
Table 30-43 shows an example of how to compute the t
pasc
delay.
The PCSS signal is not supported when Continuous Serial Communication SCK is enabled
(CONT_SCKE=1).
30.5.2.8 SPI Transfer Formats
The SPI serial communication is controlled by the Serial Communications Clock (SCK) signal and the
PCS signals. The SCK signal provided by the Master device synchronizes shifting and sampling of the data
on the SI and SO pins. The PCS signals serve as enable signals for the slave devices.
Table 30-42. Peripheral Chip Select Strobe Assert Computation Example
PCSSCK Prescaler Fsys Delay before Transfer
0b11 7 100 MHz 70.0 ns
Table 30-43. Peripheral Chip Select Strobe Negate Computation Example
PASC Prescaler Fsys Delay after Transfer
0b11 7 100 MHz 70.0 ns
t
PCSSCK
1
f
SYS
----------
PCSSCK=
t
PASC
1
f
SYS
----------
PASC=
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