NXP Semiconductors MPC5606S - Stop Mode

Interrupt Controller (INTC)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 755
21.4.1.4 Stop mode
The INTC supports stop mode. The INTC can have its clock input disabled at any time by the clock driver
on the device. While its clocks are disabled, the INTC registers are not accessible.
The INTC requires clocking in order for a peripheral interrupt request to generate an interrupt request to
the processor. Since the INTC is not clocked in stop mode, peripheral interrupt requests cannot be used as
a wakeup source, unless the clock, reset, and power module (CRP) supports that interrupt request as a
wakeup source.
21.5 Memory map and register description
21.5.1 Module memory map
Table 21-2 shows the INTC memory map.
21.5.2 Register description
With exception of the INTC_SSCIn and INTC_PSRn, all registers are 32 bits in width. Any combination
of accessing the four bytes of a register with a single access is supported, provided that the access does not
Table 21-2. INTC memory map
Offset from
INTC_BASE_
ADDR
1
1
INTC_BASE_ADDR = 0xFFF4_8000
Register Access
Reset
Value
Location
0x0000 INTC_MCR—INTC module configuration register R/W 0x0000_0000 on page 756
0x0004 Reserved
0x0008 INTC_CPR—INTC current priority register R/W 0x0000_000F on page 756
0x00C Reserved
0x0010 INTC_IACKR—INTC interrupt acknowledge register R
2
/W
2
When the HVEN bit in the INTC module configuration register (INTC_MCR) is asserted, a read of the INTC_IACKR
has no side effects.
0x0000_0000 on page 758
0x0014 Reserved
0x0018 INTC_EOIR—INTC end of interrupt register W 0x0000_0000 on page 759
0x001C Reserved
0x0020–
0x0027
INTC_SSCIR[0:7]—INTC software set/clear interrupt
register [0:7]
R/W 0x0000_0000 on page 759
0x0028–
0x003C
Reserved
0x0040–
0x010C
INTC_PSRn -INTC priority select register [0:206]
3
3
The PRI fields are “reserved” for peripheral interrupt requests whose vectors are labeled as Reserved in
Figure 21-3
R/W 0x0000_0000 on page 761