NXP Semiconductors MPC5606S - Page 763

Interrupt Controller (INTC)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 761
21.5.2.6 INTC Priority Select Registers (INTC_PSR0_3–INTC_PSR204_207)
Offset: 0x0040 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
0 0 0 0 PRI0 0 0 0 0 PRI1
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
0 0 0 0 PRI2 0 0 0 0 PRI3
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 21-8. INTC Priority Select Register 0–3 (INTC_PSR[0:3])
Offset: 0x00D0 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
0 0 0 0 PRI204 0 0 0 0 PRI205
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
0 0 0 0 PRI206 0 0 0 0 0 0 0 0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 21-9. INTC Priority Select Register 204-206 (INTC_PSR[204:206])
Table 21-8. INTC_PSR0_3–INTC_PSR204-206 field descriptions
Field Description
4–7, 12–15,
20–23, 28–31
PRI[0:3]–
PRI204:206
Priority Select. PRIx selects the priority for interrupt requests. Refer to Section 21.6, Functional
description.
Table 21-9. INTC Priority Select Register Address Offsets
INTC_PSRx_x Offset Address INTC_PSRx_x Offset Address
INTC_PSR0_3 0x0040 INTC_PSR104_107 0x00A8
INTC_PSR4_7 0x0044 INTC_PSR108_111 0x00AC
INTC_PSR8_11 0x0048 INTC_PSR112_115 0x00B0