Mode Entry Module (MC_ME)
MPC5606S Microcontroller Reference Manual, Rev. 7
938 Freescale Semiconductor
flashes can be put in power-down mode as needed. If there is a Halt mode request while an interrupt request
is active, the device mode does not change, and an invalid mode interrupt is not generated.
This mode is intended as a first level low-power mode with
• The core clock frozen
• Only a few peripherals running
and to be used by software
• To wait until it is required to do something and then to react quickly (i.e. within a few system clock
cycles of an interrupt event)
All power domains except power domains #0 and #1 are configurable in this mode in order to reduce
leakage consumption. Active power domains are determined by the power configuration register
PCU_PCONF2 of the MC_PCU.
NOTE
If Halt is configured with ME_HALT_MC[MVRON] = 0,
ME_HALT_MC[FIRCON] = 0, and
ME_HALT_MC[SYSCLK] = 0010/0011, the Main VREG will
nevertheless remain enabled during the Halt mode if the previous Run[0..3]
mode is configured with ME_RUN[0..3]_MC[FXOSCON] = 1.
25.4.2.7 Stop mode
The device enters this mode on the following events:
• From one of the Run0…3 modes when the TARGET_MODE bit field of the ME_MCTL register
is written with “1010”.
As soon as any of the above events occur, a Stop mode transition request is generated. The mode
configuration information for this mode is provided by the ME_STOP_MC register. This mode is fully
configurable, and the ME_STOP_MC register should be programmed according to the system needs. The
FMPLL0 is switched off in this mode. The flashes can be put in power-down mode as needed. If there is
a Stop mode request while any interrupt or wakeup event is active, the device mode does not change, and
an invalid mode interrupt is not generated.
This can be used as an advanced low-power mode with the core clock frozen and almost all peripherals
stopped.
This mode is intended as an advanced low-power mode with
• The core clock frozen
• Almost all peripherals stopped
and to be used by software
• To wait until it is required to do something with no need to react quickly (e.g. allow for system
clock source to be re-started)
If the pads’ power sequence driver cell needs to be disabled while entering this mode, the PDO bit of the
ME_STOP_MC register should be set. The state of the outputs is kept.
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