Quad Serial Peripheral Interface (QuadSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
1034 Freescale Semiconductor
State transitions from Running to Stopped occur on the next frame boundary if a transfer is in progress, or
on the next system clock cycle if no transfers are in progress.
30.5.2.2 Master mode
In SPI Master mode (MSTR bit in the QSPI_MCR is set) the QuadSPI operates as bus master and initiates
the serial transfers by controlling the Serial Communications Clock (SCK) and the Peripheral Chip Select
(PCS) signals. The SPI command field CTAS in the executing TX FIFO entry determines which CTAR
register will be used to set the transfer attributes and which PCS signal to assert. The command fields also
contains various bits that help with queue management and transfer protocol. See Section 30.4.3.7, PUSH
TX FIFO Register (QSPI_PUSHR). for details on the SPI command fields. The data field in the executing
TX FIFO entry is loaded into the shift register and shifted out on the Serial Out (SO) pin. In SPI Master
mode, each SPI frame to be transmitted has a command associated with it allowing for transfer attribute
control on a frame by frame basis.
30.5.2.3 Slave mode
In SPI Slave mode (MSTR bit in the QSPI_MCR register is not set) the QuadSPI responds to transfers
initiated by an external SPI bus master and cannot initiate transfers. The QuadSPI slave is selected by a
bus master by having the slave’s SS asserted. In Slave mode the SCK is provided by the bus master. All
transfer attributes are controlled by the bus master but clock polarity, clock phase and numbers of bits to
transfer must still be configured in the QuadSPI slave for proper communications with an external SPI
master. In SPI Slave mode, the slave transfer attributes are set in the QSPI_CTAR0. The QuadSPI transfers
the MSB first. The LSBFE field of the associated CTAR is ignored.
30.5.2.4 FIFO Disable Operation
The FIFO disable mechanisms allow SPI transfers without using the TX FIFO or RX FIFO. The QuadSPI
operates as a double-buffered simplified SPI when the FIFOs are disabled. The TX and RX FIFOs are
disabled separately. The TX FIFO is disabled by writing a 1 to the DIS_TXF bit in the QSPI_MCR. The
RX FIFO is disabled by writing a 1 to the DIS_RXF bit in the QSPI_MCR.
The FIFO Disable mechanisms are transparent to the user and to host software; Transmit data and
commands are written to the QSPI_PUSHR and received data is read from the QSPI_POPR.
When the TX FIFO is disabled the TFFF, TFUF and TXCTR fields in QSPI_SPISR behave as if there is
a one-entry FIFO but the contents of the QSPI_TXFR registers and TXNXTPTR are undefined. When the
RX FIFO is disabled the RFDF, RFOF and RXCTR fields in the QSPI_SPISR behave as if there is a
one-entry FIFO but the contents of the QSPI_RXFR registers and POPNXTPTR are undefined.
30.5.2.5 Transmit First In First Out (TX FIFO) Buffering Mechanism
The TX FIFO functions as a buffer of SPI data and SPI Commands for transmission. The TX FIFO holds
in total 15 entries, each consisting of a command field and a data field. SPI Commands and data are added
to the TX FIFO by writing to the
PUSH TX FIFO Register (QSPI_PUSHR). TX FIFO entries can only be
removed from the TX FIFO by being shifted out or by flushing the TX FIFO.
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