Deserial Serial Peripheral Interface (DSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
324 Freescale Semiconductor
Refer to Section 11.7.2.3, DSPI Clock and Transfer Attributes Registers 0–7 (DSPIx_CTARn).
In Figure 11-20, time ‘A’ shows the one clock interval. Time ‘B’ is user programmable from a minimum
of two system clocks.
Figure 11-20. Polarity switching between frames
11.8.6 Continuous serial communications clock
The DSPI provides the option of generating a continuous SCK signal for slave peripherals that require a
continuous clock.
Continuous SCK is enabled by setting the CONT_SCKE bit in the DSPIx_MCR. Continuous SCK is valid
in all configurations.
Continuous SCK is only supported for CPHA = 1. Setting CPHA = 0 is ignored if the CONT_SCKE bit is
set. Continuous SCK is supported for modified transfer format.
Clock and transfer attributes for the continuous SCK mode are set according to the following rules:
• The TX FIFO must be cleared before initiating any SPI configuration transfer.
• When the DSPI is in SPI configuration, CTAR0 shall be used initially. At the start of each SPI
frame transfer, the CTAR specified by the CTAS for the frame should be CTAR0.
• In all configurations, the currently selected CTAR shall remain in use until the start of a frame with
a different CTAR specified, or the Continuous SCK mode is terminated.
• To ensure PCS stability during data transmission in Continuous Selection Format and with
Continuous SCK clock enabled, make sure that the data with reset CONT bit is written to
DSPI_PUSHR register before the previous data sub-frame (with CONT bit set) transfer is over.
• If multiple CTARs are used in Continuous Peripheral Chip Select mode, ensure that the following
conditions are met: if DSPIx_CTARn[CPHA]
= 1 and DSPIx_MCR[CONT_SCKE] = 0, then
ensure that DSPIx_CTARn[CPOL, CPHA, PCSSCK, or PBR] bits do not change between frames.
If DSPIx_CTARn[CPHA]
= 0 or DSPIx_MCR[CONT_SCKE] = 1, then ensure that no bit field of
DSPIx_CTARn changes between frames except DSPIx_CTARn[PBR].
• When in Continuous SCK mode, CTAR0 should always be used for the SPI transfer, and the
TX
FIFO must be clear using the MCR[CLR_TXF] field before initiating transfer.
CS
System clock
SCK
Frame 1
Frame 0
CPOL = 0 CPOL = 1
AB
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