Deserial Serial Peripheral Interface (DSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 325
The device is designed to use the same baud rate for all transfers made while using the continuous SCK.
Switching clock polarity between frames while using continuous SCK can cause errors in the transfer.
Continuous SCK operation is not guaranteed if the DSPI is put into Module Disable mode.
Enabling continuous SCK disables the CS to SCK delay and the after SCK delay. The delay after transfer
is fixed at one SCK cycle. Figure 11-21 shows timing diagram for continuous SCK format with continuous
selection disabled.
Figure 11-21. Continuous SCK timing diagram (CONT= 0)
If the CONT bit in the TX FIFO entry is set, CS remains asserted between the transfers when the CS signal
for the next transfer is the same as for the current transfer. Under certain conditions, SCK can continue
with PCS asserted, but with no data being shifted out of SOUT (SOUT pulled high). This can cause the
slave to receive incorrect data. Those conditions include:
• Continuous SCK with CONT bit set, but no data in the transmit FIFO
• Continuous SCK with CONT bit set and entering Stopped state (refer to Section 11.8.2, Start and
stop of DSPI transfers)
• Continuous SCK with CONT bit set and entering Stop mode or Module Disable mode
Figure 11-22 shows timing diagram for continuous SCK format with continuous selection enabled.
Figure 11-22. Continuous SCK timing diagram (CONT=1)
SCK
(CPOL = 0)
CS
SCK
(CPOL = 1)
Master SOUT
t
DT
t
DT
= 1 SCK.
Master SIN
SCK
(CPOL = 0)
SCK
(CPOL = 1)
Master SOUT
Master SIN
Transfer 1 Transfer 2
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