NXP Semiconductors MPC5606S - DMA Clear Enable Request (DMACERQ) Register

Enhanced Direct Memory Access (eDMA)
MPC5606S Microcontroller Reference Manual, Rev. 7
486 Freescale Semiconductor
15.3.1.6 DMA Clear Enable Request (DMACERQ) register
The DMACERQ register provides a simple memory-mapped mechanism to clear a given bit in the
DMAERQ{H,L} registers to disable the DMA request for a given channel. The data value on a register
write causes the corresponding bit in the DMAERQ{H,L} register to be cleared. A data value of 64 to 127
(regardless of the number of implemented channels) provides a global clear function, forcing the entire
contents of the DMAERQ{H,L} to be zeroed, disabling all DMA request inputs. If bit 0 (NOP) is set, the
command is ignored. This allows multiple byte registers to be written as a 32-bit word. Reads of this
register return all zeroes. See Figure 15-9 and Table 15-7 for the DMACERQ definition.
15.3.1.7 DMA Set Enable Error Interrupt (DMASEEI) register
The DMASEEI register provides a simple memory-mapped mechanism to set a given bit in the
DMAEEI{H,L} registers to enable the error interrupt for a given channel. The data value on a register
write causes the corresponding bit in the DMAEEI{H,L} register to be set. A data value of 64 to 127
Address: Base + 0x0018 Access: User write-only
0 1 2 3 4 5 6 7
R 0 0 0 0 0 0 0 0
W NOP SERQ
Reset 0 0 0 0 0 0 0 0
Figure 15-8. DMA Set Enable Request (DMASERQ) register
Table 15-6. DMA Set Enable Request (DMASERQ) field descriptions
Name Description
NOP No Operation
0 Normal operation.
1 No operation, ignore bits 6-0
SERQ[0:6] Set Enable Request
0-63 Set the corresponding bit in DMAERQ{H,L}
64-127 Set all bits in DMAERQ{H,L}
Address: Base + 0x0019 Access: User write-only
0 1 2 3 4 5 6 7
R 0 0 0 0 0 0 0 0
W NOP CERQ[0:6]
Reset 0 0 0 0 0 0 0 0
Figure 15-9. DMA Clear Enable Request (DMACERQ) register
Table 15-7. DMA Clear Enable Request (DMACERQ) field descriptions
Name Description
NOP No Operation
0 Normal operation.
1 No operation, ignore bits 6-0
CERQ[0:6] Clear Enable Request
0-63 Clear corresponding bit in DMAERQ{H,L}
64-127 Clear all bits in DMAERQ{H,L}