NXP Semiconductors MPC5606S - Global Protection Register

Display Control Unit (DCU)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 395
Figure 12-47. FG0_bcolor Register
12.3.4.39 Global Protection Register
Figure 12-48 represents the Global Protection register.
Figure 12-48. Global Protection Register
Offset:
0x254 (FG0_BCOLOR)
0x25C (FG1_BCOLOR)
0x264 (FG2_BCOLOR)
0x26C (FG3_BCOLOR)
0x274 (FG4_BCOLOR)
0x27C (FG5_BCOLOR))
0x284 (FG6_BCOLOR)
0x28C (FG7_BCOLOR)
0x294 (FG8_BCOLOR)
0x29C (FG9_BCOLOR)
0x2A4 (FG10_BCOLOR)
0x2AC (FG11_BCOLOR)
0x2B4 (FG12_BCOLOR)
0x2BC (FG13_BCOLOR)
0x2C4 (FG14_BCOLOR)
0x2CC (FG15_BCOLOR) Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0
FG0_BCOLOR[0:7]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
FG0_BCOLOR[8:23]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 12-42. FG0_bcolor field descriptions
Field Description
8–31
FG0_BCOLOR
Background color for layer FG0 for pre-blending engine
Offset: 0x300 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
HLB
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0