NXP Semiconductors MPC5606S - Legacy Modes-Separate Blanking and Integration Phase

Stepper Stall Detect (SSD)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 1183
36.6.5 Legacy modes—separate blanking and integration phase
Despite the automatic BIS it is still possible to use the SSD block in a way similar to the old design.
Separate blanking and integration phases can be obtained very easily by setting the down counter preload
value for the undesired phase to 0x0000. When the corresponding BIS is executed this phase is simply
skipped.
Note that in this case the BLNIF bit will be important for the user because its assertion marks the end of
the blanking phase.
To ease the programming of separate BLNCNTLD and ITGCNTLD register values on-the-fly the two
adjacent registers are placed into one single 32-bit access. Therefore the user who wants to implement
programmed-control switching between blanking and integration needs only one single 32-bit register
write (to switch the down counter preload values) prior to the execution of the blanking or integration
phase.