Clock Description
MPC5606S Microcontroller Reference Manual, Rev. 7
204 Freescale Semiconductor
8.4.4 Functional description
8.4.4.1 System clock generation
Figure 8-13 shows the block diagram of the system clock generation logic. The MC_ME provides the
system clock select and switch mask (see Chapter 25, Mode Entry Module (MC_ME), for more details),
and the MC_RGM provides the safe clock request (see Chapter 31, Reset Generation Module
(MC_RGM), for more details). The safe clock request forces the selector to select the 16 MHz internal RC
oscillator as the system clock and to ignore the system clock select.
8.4.4.1.1 System clock source selection
During normal operation, the system clock selection is controlled by:
• MC_RGM on a Safe mode event
• MC_ME in all other cases
8.4.4.1.2 System clock disable
During normal operation, the system clock can be disabled by the MC_ME.
8.4.4.1.3 System clock dividers
The MC_CGM generates three derived clocks from the system clock that are used as the reference clocks
for their associated peripherals.
8.4.4.2 Auxiliary clock generation
Figure 8-14 (and those following) shows the block diagram of the auxiliary clock generation logic. See
Section 8.4.3.1.5, Auxiliary Clock 0 Select Control Register (CGM_AC0_SC), Section 8.4.3.1.6,
Auxiliary Clock 1 Select Control Register (CGM_AC1_SC), Section 8.4.3.1.8, Auxiliary Clock 2 Select
Control Register (CGM_AC2_SC), and Section 8.4.3.1.10, Auxiliary Clock 3 Select Control Register
(CGM_AC3_SC), for auxiliary clock selection control.
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