Clock Description
MPC5606S Microcontroller Reference Manual, Rev. 7
222 Freescale Semiconductor
Figure 8-26. Diagram of progressive clock switching
8.9.6.3 Normal mode with frequency modulation
The FMPLL default mode is without frequency modulation enabled. When frequency modulation is
enabled, however, two parameters must be set to generate the desired level of modulation: the period and
the step. The modulation waveform is always a triangle wave and its shape is not programmable.
FM modulation is activated in two steps:
1. Configure the FM modulation characteristics: MOD_PERIOD, INC_STEP.
2. Enable the FM modulation by programming the FM_EN bit of MR register to 1. FM modulated
mode can be enabled only when the PLL is in lock state.
To latch these values inside the PLL, two ways are used, depending on the value of the STRB_BYPASS
register bit in MR.
If STRB_BYPASS is low, the modulation parameters are latched in the PLL only when the STRB signal
goes high for at least two cycles of the INFIN clock. The STRB signal is automatically generated in the
PLLD when the modulation is enabled (FM_EN goes high) if the PLL is locked (s_lock = 1) or when the
modulation has been enabled (FM_EN = 1) and PLL enters in lock state (s_lock goes high).
If STRB_BYPASS is high, the STRB signal is bypassed. In this case, control bits (MOD_PERIOD[12:0],
INC_STEP[14:0], SPREAD_CONTROL) need to be static or hardwired to constant values. The control
bits must be changed only when the PLL is in power down mode.
The modulation depth in % is
NOTE
You must ensure that the value of MODPERIOD does not exceed 0x1000
and that the product of INCTEP and MODPERIOD is less than (2
15
– 1).
ck_pll_out ck_pll_div
8
4
2
1
ModulationDepth
100 5 INCSTEPxMODPERIOD
2
15
1–MDF
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