Safety
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 123
4.2.5.3 SWT Interrupt Register (SWT_IR)
The SWT_IR contains the timeout interrupt flag.
Table 4-7. SWT_CR field descriptions
Field Description
MAPn Master Access Protection for Master n. The platform bus master assignments are device specific.
0 Access for the master is not enabled
1 Access for the master is enabled
KEY Keyed Service Mode.
0 Fixed Service Sequence. The fixed sequence 0xA602, 0xB480 is used to service the watchdog.
1 Keyed Service mode. Two pseudorandom key values are used to service the watchdog.
RIA Reset on Invalid Access.
0 Invalid access to the SWT generates a bus error
1 Invalid access to the SWT causes a system reset if WEN=1
WND Window mode.
0 Regular mode, service sequence can be done at any time
1 Windowed mode, the service sequence is only valid when the down counter is less than the value in
the SWT_WN register.
ITR Interrupt Then Reset.
0 Generate a reset on a timeout
1 Generate an interrupt on an initial timeout, reset on a second consecutive timeout
HLK Hard Lock. This bit is only cleared at reset.
0 SWT_CR, SWT_TO and SWT_WN are read/write registers if SLK=0
1 SWT_CR, SWT_TO and SWT_WN are read only registers
SLK Soft Lock. This bit is cleared by writing the unlock sequence to the service register.
0 SWT_CR, SWT_TO and SWT_WN are read/write registers if HLK=0
1 SWT_CR, SWT_TO and SWT_WN are read only registers
CSL Clock Selection. Selects the LP IRC 128 khz oscillator clock that drives the internal timer.
CSL bit can be written.The status of the bit has no effect on counter clock selection on this device.
0 System clock. (Not applicable on this device)
1 Oscillator clock.
FRZ Freeze available during debug. This function is only operational when the CPU is in an active debug
mode.
0 SWT counter continues to run independent of the CPU status
1 SWT counter is stopped when the CPU is stopped by a debugger
WEN Watchdog Enabled.
0 SWT is disabled
1 SWT is enabled
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