NXP Semiconductors MPC5606S - Parallel GPIO Pad Data in Register (PGPDI0-PGPDI4)

System Integration Unit Lite (SIUL)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 1205
37.5.3.13 Parallel GPIO Pad Data In Register (PGPDI0–PGPDI4)
These registers hold the synchronized input value from the pads.
Address: Base + 0x0C40–0x0C50 (5 registers) Access: User read
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R PPDI[x][15:0]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R PPDI[x+1][15:0]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 37-16. Parallel GPIO Pad Data In Register (PGPDI0)
Table 37-16. PGPDI field descriptions
Field Description
PPDI[x] Parallel Pad Data In
Read the current pad value.
Accesses to this register location are coherent with accesses to the bit-wise GPIO Pad Data Input
Registers (GPDI0_3–GPDI132_135).
The x and bit index define which PPDI register bit is equivalent to which PDI register bit according
to the following equation:
PPDI[x][y] = PDI[(x*16)+y]