NXP Semiconductors MPC5606S - Page 1208

System Integration Unit Lite (SIUL)
MPC5606S Microcontroller Reference Manual, Rev. 7
1206 Freescale Semiconductor
37.5.3.14 Masked Parallel GPIO Pad Data Out Register (MPGPDO0–MPGPDO8)
This register can be used to selectively modify the pad values associated to PPDO[x][15:0]. The
MPGPDO[x] register may only be accessed with 32-bit writes. 8-bit or 16-bit writes will not modify any
bits in the register and cause a transfer error response by the module. Read accesses will return 0.
Address: Base + 0x0C80–0x0CA4 (9 registers) Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W MASK[x][15:0]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W MPPDO[x][15:0]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 37-17. Masked Parallel GPIO Pad Data Out Register (MPGPDO0)
Table 37-17. MPGPDO0_3 field descriptions
Field Description
MASK[x]
[15:0]
Mask Field
Each bit corresponds to one data bit in the MPPDO[x] register at the same bit location.
0 The associated bit value in the MPPDO[x] field is ignored
1 The associated bit value in the MPPDO[x] field is written
MPPDO[x]
[15:0]
Masked Parallel Pad Data Out
Write the data register that stores the value to be driven on the pad in output mode.
Accesses to this register location are coherent with accesses to the bit-wise GPIO Pad Data
Output Registers (GPDO0_3–GPDO132_135).
The x and bit index define which MPPDO register bit is equivalent to which PDO register bit
according to the following equation:
MPPDO[x][y] = PDO[(x*16)+y]